1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having data of a selected memory cell read internally using a sense amplifier. More specifically, the present invention relates to the configuration for optimizing an activation timing of the sense amplifier.
2. Description of the Background Art
There is known, as a semiconductor memory device, a static memory (SRAM: Static Random Access Memory) having internal circuitry operating statically. Since the internal circuitry of the SRAM operates statically, and a memory cell row and a memory cell column are selected substantially at the same time, the SRAM can ensure high speed access and is widely used for high speed processing.
FIG. 34 is a schematic diagram showing the configuration of a main part of a conventional SRAM. In FIG. 34, SRAM cells MC are arranged in rows and columns in a memory array. In FIG. 34, SRAM cells MC are arranged in (m+1) rows and (n+1) columns. Word lines WL0 to WLm are arranged in correspondence to the respective rows of SRAM cells MC, and bit line pairs BL0, ZBL0 to BLn, ZBLn are arranged in correspondence to the respective columns of SRAM cells MC.
Word line drivers WD0 to WDm are arranged in correspondence to word lines WL0 to WLm, respectively, and column select gates CSG0 to CSGn are arranged in correspondence to bit line pairs BL0, ZBL0 to BLn, ZBLn, respectively.
Word line drivers WD0 to WDm, each of which is formed of an inverter, drive word lines WL0 to WLm in accordance with word line select signals WX0 to WXm generated on the basis of an X address signal, respectively. Accordingly, when selected, word line select signals WX0 to WXn are at L level (logical low level) and a selected word line is driven to H level (logical high level).
Column select gates CSG0 to CSGn are made conductive in accordance with column select signals Y0 to Yn generated on the basis of a Y address signal, respectively, and couple corresponding bit line pairs BL0, ZBL0 to BLn, ZBLn to an internal bus DB, respectively, when made conductive. Internal bus DB includes internal bus lines DBL and ZDBL transferring complementary data signals, respectively.
A sense amplifier SA that differentially amplifies signals on complementary data bus lines DBL and ZDBL of internal data bus DB, is provided to internal data bus DB. Sense amplifier SA differentially amplifies complementary data signals transferred from selected bit lines to internal data bus DB and generates internal read data DO in response to activation of a sense enable signal SE from a delay adjustment element DLE.
Delay adjustment element DLE, which is formed of, for example, cascaded delaying inverters, adjusts the delay time of a sense trigger signal SATR and generates sense enable signal SE. Sense trigger signal SATR applied to delay adjustment element DLE is generated on the basis of either a bit line precharge signal or a word line activation signal when data is read.
Sense amplifier SA is provided in correspondence to a predetermined number of bit line pairs. Specifically, this memory cell array is divided into a plurality of column blocks in accordance with the number of internal read data bits. Sense amplifiers SA are arranged in correspondence to the respective column blocks, and sense enable signal SE from delay adjustment element DLE is commonly applied to sense amplifiers SA which are arranged in correspondence to the respective column blocks. Now, the operation of the SRAM shown in FIG. 34 in data read will be briefly described.
In accordance with an X address signal, one of word line select signals WX0 to WXm is driven into a selected state. Word line WL designated by this X address signal is driven into a selected state by corresponding one of word line drivers WD0 to WDm, and the stored data of SRAM cells MC connected to selected word line WL is read to corresponding bit line pairs BL0, ZBL0 to BLn, ZBLn. SRAM cell MC has the configuration as will be described later, and stores complementary data at internal storage nodes, respectively. The potential of one bit line of each of bit line pairs BL0, ZBL0 to BLn, ZBLn becomes lower than a precharge potential in accordance with L level data. Here, all of bit line pairs BL0, ZBL0 to BLn, ZBLn are precharged to power supply voltage level in a standby state.
In SRAM, the X address signal and the Y address signal are applied in parallel. A column select operation is performed in parallel to a word line select operation. In accordance with the Y address signal, one of column select signals Y0 to Yn is driven into a selected state, one of column select gates CSG0 to CSGn corresponding to a selected column is made conductive responsively, and the bit line pair on the selected column are connected to data bus lines DBL and ZDBL of internal data bus DB, respectively.
When a certain time passes since selection of the word line, the potential difference between the selected bit lines is developed and the potential difference in internal data bus DB is developed accordingly and reaches a potential difference which can be sensed by sense amplifier SA. Delay adjustment element DLE adjusts the sense timing of sense amplifier SA. When the potential difference of internal data bus DB becomes sufficiently large, delay adjustment element DLE activates sense enable signal SE to start the sensing operation of sense amplifier SA. Sense amplifier SA differentially amplifies the complementary data signals on internal data bus DB and generates internal read data DO.
FIG. 35 shows an example of the configuration of sense amplifier SA shown in FIG. 34. In FIG. 35, sense amplifier SA includes: cross-coupled P-channel MOS transistors (insulating gate field effect transistors) PQa and PQb; cross-coupled N-channel MOS transistors NQa and NQb; a P-channel MOS transistor PQc for coupling a sense node SNa to internal data bus line DBL in response to sense enable signal SE; a P-channel MOS transistor PQd for coupling a sense node SNb to an internal data bus line ZDBL in response to sense enable signal SE; and an N-channel MOS transistor NQc for coupling the sources of MOS transistors NQa and NQb to a ground node in accordance with sense enable signal SE.
P-channel MOS transistor PQa is connected between a power supply node and sense node SNa, and has a gate thereof connected to sense node SNb. P-channel MOS transistor PQb is connected between the power supply node and sense node SNb, and has a gate thereof connected to sense node SNb. N-channel MOS transistor NQa is connected between sense node SNa and MOS transistor NQc, and has a gate thereof connected to sense node SNb. N-channel MOS transistor NQb is connected between sense node SNb and MOS transistor NQc, and has a gate thereof connected to sense node SNa.
Internal data bus lines DBL and ZDBL are 1-bit data bus lines included in data bus DB shown in FIG. 34, and coupled to a selected bit line pair through the column select gate in data read, respectively.
Sense amplifier SA further includes a holding circuit HK for latching the signals at sense nodes SNa and SNb and generating internal read data DO. The operation of sense amplifier SA shown in FIG. 35 will now be described with reference to a timing chart shown in FIG. 36.
When data is read, bit lines BBL and ZBL are precharged to power supply voltage level by a bit line load circuit, not shown. In accordance with the X address signal, the potential of word line WL corresponding to an addressed row rises to H level, the data of memory cells MC connected to this selected word line is read to bit lines BL and ZBL. In SRAM cell MC, complementary data of H-level data and L-level data are stored in a pair of storage nodes, respectively. The bit line connected to the storage node storing the L-level data is discharged through the driver transistor of memory cell MC and the voltage level of the bit line is lowered.
In parallel to this word line select operation, a column select operation is performed. Bit lines BL and ZBL corresponding to a selected column are connected to internal data bus lines DBL and ZDBL, respectively. Since sense enable signal SE is at L level, MOS transistors PQc and PQd are rendered conductive and the potential changes of bit lines BL and ZBL are transmitted to sense nodes SNa and SNb, respectively. As indicated at time ta, if the potential difference between sense nodes SNa and SNb is small, a sense margin is small and sense amplifier SA may possibly malfunction.
However, at time tb, the potential difference between bit lines BL and ZBL is sufficiently developed and the potential difference between sense nodes SNa and SNb is sufficiently developed, accordingly. Then, sense enable signal SE is activated. Accordingly, in sense amplifier SA, MOS transistors PQc and PQd enter a nonconductive state, sense enable signal SE applied at the gate of MOS transistor NQc attains H level, and sense amplifier SA is activated.
When sense amplifier SA is activated, sense nodes SNa and SNb are disconnected from internal data bus lines DBL and ZDBL, respectively. Accordingly, sense amplifier SA performs a sensing operation at high speed in accordance with a xe2x80x9ccharge confinementxe2x80x9d scheme, and differentially amplifies the potential difference generated between sense nodes SNa and SNb, whereby the sense node at high voltage level is driven to power supply voltage level and that at low voltage level is driven to ground voltage level. While sense enable signal SE is active, sense amplifies SA latches the amplified data at sense nodes SNa and SNb.
Holding circuit HK latches the data of sense nodes SNa and SNb and generates internal read data DO. Holding circuit HK may latch the data of sense nodes SNa and SNb in response to, for example, a timing signal such as sense enable signal SE, or may be formed of a latch circuit such as an inverter latch. By utilizing holding circuit HK, it is intended to adjust a data output timing and to secure an output data definite period.
When activated, sense amplifier SA latches the amplified data at nodes SNa and SNb. Therefore, sense amplifier SA is referred to as xe2x80x9clatch type sense amplifierxe2x80x9d. Where this latch type sense amplifier is employed in place of a general current mirror type sense amplifier, the following advantages can be obtained. As the integration degree of a semiconductor integrated circuit is improved following the development of a processing technique to miniaturization, it is strongly demanded to reduce power consumption in view of prevention of malfunction caused by heat generation and other(s). This is true for a memory such as SRAM. If a current mirror type sense amplifier is utilized, a current source is necessary. While data is held, a steady current flows to increase current consumption. However, latch type sense amplifier SA causes a current flow only during a sensing operation of differentially amplifying the voltages of sense nodes SNa and SNb. No current flows after sense nodes SNa and SNb are driven to the levels of a power supply voltage VCC and a ground voltage. Therefore, compared with a current mirror type sense amplifier, latch type sense amplifier SA can greatly reduce power consumption.
Further, during the sensing operation, sense amplifier SA is only required to drive sense nodes SNa and SNb due to isolation of sense nodes SNa and SNB from internal data bus DB. Therefore, sense amplifier SA can drive small load at high speed, and therefore, can perform the sensing operation at high speed with low current consumption.
To optimize the operation timing of sense amplifier SA for performing a sensing operation at a faster timing with a sufficient sense margin, delay adjustment element DLE shown in FIG. 34 is provided.
Latch type sense amplifier SA has a feature of large gain, in addition to the advantage that no direct current flows after data amplification operation. As the gain is larger, sense amplifier SA can sense the potential difference between the bit lines even if the potential difference is very small. However, once sense amplifier SA senses and amplifies data, latch type sense amplifier SA turns into a latching state and, therefore, the sensed/amplified data cannot be corrected.
Therefore, if a sensing operation is started at, for example, time ta shown in FIG. 36 before the potential difference between the bit lines, i.e., between sense nodes SNa and SNb becomes sufficiently large, latch type sense amplifier SA might possibly sense data accurately due to a variation in the characteristics of the transistors constituting sense amplifier SA, and the influence of noise generated on a bit line. To prevent such erroneous reading, delay adjustment element DLE activates sense enable signal SE at time tb at which the potential difference between the bit lines is sufficiently developed. However, if time tb at which this sensing operation starts is late, the data read rate decreases and high rate data reading cannot be achieved.
Therefore, a method of finely adjusting the activation timing of sense enable signal SE by using delay adjustment element DLE shown in FIG. 34 is generally employed. However, with delay adjustment element DLE, if the potential difference between the bit lines changes due to variation in memory cell transistor characteristics after manufacturing, a correct sense timing cannot be set. If such a variation is considered, it is necessary to determine an activation timing for activating sense enable signal SE on the assumption of the worst case. If the worst case is assumed, the sense activation timing is delayed and high speed data read cannot be achieved,
To solve such problem, there is proposed a method of reflecting a variation in memory cell transistor characteristics in generation of sense enable activation timing utilizing dummy cells, as disclosed in, for example, Japanese Patent Laying-Open No. 9-259589. According to this prior art reference, dummy cells are arranged corresponding to the rows of normal memory cells, and the load (parasitic capacitance) of the bit line arranged for the dummy cells are made equal to that of the bit line connected to the normal memory cells. Word lines are common to the normal memory cells and the dummy memory cells.
Therefore, the potential changing rate of a dummy bit line becomes equal to that of a normal bit line, so that the potential of the dummy bit line is sensed for activating a sense amplifier. A dummy cell and a normal memory cell share a word line and are equal in delay time required until selection of a word line. Thus, when the sensing operation of the sense amplifier starts, the potential difference between a normal bit line pair is, for example, VDD/2 similar to that between the dummy bit lines, and is transmitted to the sense amplifier. Thus, the sense amplifier can perform a sensing operation while securing a sufficient sense margin.
However, by employing latch type sense amplifier SA, an accurate sensing operation can be achieved to differentially amplify the potential difference between the bit lines even if the potential difference is not more than VCC/2 because of the large gain of sense amplifier SA. Therefore, according to the method of the prior art reference, the sense margin becomes unnecessarily great, making it impossible to generate internal data at high speed. Besides, since the amplitude of each bit line is made unnecessarily large, a bit line charging current increases and current consumption increases.
Accordingly, in order to set an optimum sense timing, it is necessary to adjust the activation timing for activating sense enable signal SE in accordance with the configuration of a memory cell array. If the number of word lines and that of bit lines change (word-bit configuration changes), it is necessary to individually adjust the activation timing of a sense amplifier for various bit and word configurations. Where an automatic generation tool such as a memory compiler is used, circuit design is made while assuming the worst case. Thus, the sense timing of the sense amplifier cannot be optimized, and it is necessary to individually adjust the activation timing of the sense amplifier, disadvantageously deteriorating design efficiency.
Further, there is disclosed in National Patent Publication No. 5-504648 the architecture in which a dummy word line is provided separately from normal word lines, and is used to drive a plurality of dummy cells simultaneously driven into a selected state for discharging the potential of a dummy bit line. According to this configuration, the dummy bit line is driven by a plurality of dummy cells, the potential change rate of the dummy bit line can be set higher than that of a normal bit line, and a sense amplifier can be activated at a timing at which the potential difference of the normal bit line pair is small.
However, with the configuration of this prior art reference, the dummy word line is provided separately from the normal word lines, and a dummy word line decoder is activated at the same timing as that for activating a normal word line decoder, to drive the dummy word line into a selected state. Therefore, it is difficult to make the selection timing equal to each other for the dummy word line and for a normal word line, and the delay time generated until the dummy cells are driven into a selected state deviates from that until the normal memory cells are driven into a selected state. This results in a disadvantage in that the sense timing of the sense amplifier cannot be accurately set.
Further, the position of the dummy word line is fixed irrespectively of the position of a selected normal word line and the potential change rate of the dummy word line is always the same. Therefore, even if a normal word line near the sense amplifier is selected and the potential change of this bit line is transmitted to the sense amplifier relatively faster, the activation timing of the sense amplifier cannot be adjusted. Thus, the sense amplifier is activated under the state of a larger potential difference between the bit lines.
Particularly in this case, the sense amplifier is activated at a different timing for a different potential difference between the sense nodes of the sense amplifier according to the position of a selected normal word line. To sufficiently secure a sense margin, therefore, it is necessary to set the sense timing at a timing for activating the sense amplifier at a minimum potential difference. This results in a disadvantage that the potential difference between the bit lines becomes larger than required when a normal word line near the sense amplifier is selected.
Therefore, the method of this prior art reference, similarly to the former prior art reference, is required to adjust variation in individual circuits after manufacturing. In addition, the method of this prior art reference has the following disadvantages. The dummy word line is extended in the same direction as the extending direction of the normal word lines. A different number of dummy cells from that of the memory cells connected to each normal word line are connected to the dummy word line. The load of each normal word line differs from that of the dummy word line. As a result, the dummy bit lines and the normal bit lines cannot be driven at the same timing, and the sense timing cannot be accurately detected.
Thus, this prior art needs to individually adjust a dummy word line drive timing if the number of bit lines is made different, i.e., a bit configuration is made different and the load of the normal word line is changed.
It is an object of the present invention to provide a semiconductor memory device capable of readily, accurately and automatically generating a sensing operation activation timing within the semiconductor memory device.
It is another object of the present invention to provide a semiconductor memory device capable of automatically generating an optimum sense enable timing irrespectively of the word-bit configuration of the semiconductor memory device.
It is still another object of the present invention to provide a semiconductor memory device capable of accurately activating a sense amplifier at an optimum timing irrespectively of variation in transistor characteristics after manufacturing.
A semiconductor memory device according to a first aspect of the present invention includes: a plurality of normal memory cells arranged in rows and columns; a plurality of normal word lines arranged in correspondence to rows of the normal memory cells, and connecting to the normal memory cells in the corresponding rows, respectively; and a plurality of dummy cells arranged in correspondence to the normal word lines separately from the corresponding normal word lines, and arranged in alignment in at least one column in a column direction. Each of the dummy cells stores data of predetermined logic level.
The semiconductor memory device according to the first aspect of the present invention further includes: a dummy bit line arranged in correspondence to the column(s) of the plurality of dummy cells, and connecting to the plurality of dummy cells; a plurality of dummy cell select circuits each arranged in correspondence to a predetermined number of the normal word lines, and each driving a corresponding predetermined number of the dummy cells arranged correspondingly into a selected state when one of a corresponding predetermined number of normal word lines is selected; and a dummy sense circuit detecting a potential of the dummy bit line, and generating a sense activation signal for providing a sense timing for sensing the data of a selected normal memory cell.
A semiconductor memory device according to a second aspect of the present invention includes: a plurality of normal memory cells accessible through a plurality of ports and arranged in rows and columns; and a plurality of first port normal word lines arranged in correspondence to rows of the normal memory cells, and connecting to the normal memory cells in the corresponding rows, respectively. A first port normal word line is selected in accordance with an address signal in an access through a first port among the plurality of ports.
The semiconductor memory device according to the second aspect of the present invention further includes: a plurality of second port normal word lines arranged in correspondence to the rows of the normal memory cells, and connecting to the normal memory cells in the corresponding rows, respectively. A second port normal word line is selected in accordance with the address signal in an access through a second port among the plurality of ports.
The semiconductor memory device according to the second aspect of the present invention further includes: a plurality of first dummy cells arranged in correspondence to and isolatedly from the first port normal word lines, and arranged being aligned in at least one column in a column direction; a plurality of second dummy cells arranged in correspondence to and being isolated from the second port normal word lines, and arranged being aligned in at least one column in the column direction; a first dummy bit line arranged in correspondence to the first dummy cells, and having the first dummy cells commonly connected thereto; a second dummy bit line arranged in correspondence to the second dummy cells, and having the second dummy cells commonly connected thereto; a plurality of first dummy cell select circuits each arranged in correspondence to a predetermined number of the first port normal word lines, and each driving a corresponding set of the first dummy cells into a selected state when one of the corresponding first port normal word lines is selected; a plurality of second dummy cell select circuits each arranged in correspondence to a predetermined number of the second port normal word lines, and each driving a corresponding set of the second dummy cells into the selected state when one of the corresponding second port normal word lines is selected; a first dummy sense circuit for detecting a voltage on the first dummy bit line and generating a first sense amplifier activation signal for activating a sense amplifier for reading data of the memory cells accessed through the first port; and a second dummy sense circuit detecting a voltage on the second dummy bit line and generating a second sense amplifier activation signal for activating a sense amplifier for reading the data of the memory cells accessed through the second port.
A set of dummy cells is provided for each predetermined number of normal word lines, and a corresponding set of dummy cells is driven into a selected state in accordance with selection of a corresponding normal word line, and the dummy bit line is driven. Therefore, it is possible to always generate a voltage change accommodating for the array configuration on the dummy bit line, and to stably set a sensing operation start timing irrespectively of the array configuration. In particular, since the voltage changing rate of the dummy bit line is higher than that of the normal bit line, it is possible to activate the sense amplifier at a faster timing and to achieve high speed data access.
Further, the dummy cells at positions corresponding to the position of a selected normal word line are driven into a selected state. Therefore, it is possible to make the voltage changing of the dummy bit line corresponding to that of the normal bit line, to accurately generate a voltage change corresponding to voltage change in the sense amplifier on the dummy bit line, and to generate a sense activation timing for this sense amplifier.
Moreover, even in a multi-port memory, by arranging dummy cells in correspondence to a predetermined number of normal word lines for each port and arranging a dummy bit line in correspondence to each port, it is possible to accurately set a sense timing for each port.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.